This invention relates generally to the manufacture of integrated circuit devices, and more specifically, to the manufacture of single and dual damascene interconnect structures in integrated circuit devices.
Several basic methods for forming a dual damascene structure have been developed. These include the via-first approach, the line-first approach, and various hardmask schemes. All of these methods are fraught with problems.
With the via-first approach, the use of photoresist layers on dielectric layers often results in “poisoning” of the line imaging layer which is done after vias are fully or partially etched into the dielectric. This is the case even when bottom anti-reflective coatings are used to fill the vias temporarily, so as to provide a planar surface for the line imaging layer. The source of this poisoning is not clearly understood, but it is thought to be due to absorption and/or generation and liberation of amine compounds from the insulator, as a result of its finite permeability and the use of N2 and H2 process gases in the films below, as well as in the etching and stripping of patterns prior to applying the photoresist where the poisoning is observed. The poisoning problem appears to be much worse when the dielectric layer is a low-k insulator applied using chemical vapor deposition (CVD), as compared to silicate glass dielectric layers. This is thought to be a result of the increased permeability of low-k insulators, the use of N2O as a carrier gas in some deposition recipes, and the common use of reducing chemistries such as N2and H2 for stripping prior lithographic patterns.
Attempts to solve the poisoning problems have been incomplete. One attempt is to use a resist material that is less sensitive to poisoning. However, such resist materials compromise imaging resolution and decrease lithographic process window. Another attempt is to modify the dielectric material so that it causes less poisoning. For example, in U.S. Pat. No. 6,147,009 to Grill et al., the use of N2O as an oxidizing carrier gas is avoided by using a siloxane-based precursor and He gas to make low-k SiCOH films, thereby eliminating a source of nitrogen in the as-deposited film. This may prevent poisoning of a first photoresist material on the blanket SiCOH film, but after the pattern is etched into the SiCOH film and the resist is stripped, amines may still be generated and may poison a subsequent photoresist patterning step such as would be required for dual damascene interconnects. In another example, U.S. Published Application No. 2001/0036748 by Rutter, Jr. et al. describes a method to eliminate poisoning of photoresist by pre-treating the low-k material with acidic compounds. However, such modifications may adversely affect the dielectric constant and other characteristics of the insulating materials. Also, certain underlying dielectric materials such as dielectric barrier caps on underlying Cu levels preferably contain nitrogen and hydrogen, and can be a source of poisoning that might not be easily remedied. Removing the nitrogen compromises the barrier properties, and removing the hydrogen raises the dielectric constant to unacceptable levels.
An example of a solution to line resist poisoning in a via-first dual-damascene approach is disclosed in K. Higashi et al., “A manufacturable Copper/Low-k SiOC/SiCN Process Technology for 90 nm-node High Performance eDRAM,” Proc. of IEEE 2002 IITC, June 2002, pp. 15–17. Their practical solution required modifying the resist itself, limiting the polish stop and etch stop (Cu barrier cap) layers to nitrogen-free films, and eliminating use of nitrogen in etch and dielectric deposition chemistries. Even when a spin-on glass (SOG) layer was added between the planarizing and imaging layers (presumably for resist budget during etch), poisoning still occurred through this SOG layer.
Another approach with partial success is to deposit a barrier material after via etch. In this approach, the via is lined with a very thin layer of a barrier material such as TEOS or silane SiO2, thereby encapsulating the poisoning source. The liner material must have excellent conformality. Since it is difficult to deposit materials in high-aspect ratio vias, this approach may not be extendable to future technologies. Defects in thin regions of this liner may allow poisoning gases to pass through, and even with low statistical occurrence may cause an unacceptable level of defective patterns in the line imaging layer.
Another approach that can successfully eliminate poisoning is through the application of multilayer hardmask films such as SiO2, Si3N4, and metal nitrides such as TaN. This concept was first described in U.S. Pat. No. 6,140,226 to Grill et al., and was used successfully by R. D. Goldblatt et al. (“A High Performance 0.13 Âμm Copper BEOL Technology with Low-k Dielectric,” Proceedings of the IEEE 2000 International Interconnect Technology Conference, pp.261–263) to pattern SiLK™ low-k polyarylene ether dielectric.(SiLK™ is a registered trademark of the Dow Chemical Company.) These methods are more complex and can be difficult for RIE manufacturing, because the RIE must be able to etch the dielectric with high selectively to the hardmask materials. That in turn may constrain the conditions under which the RIE may operate, and hence may compromise the ability to achieve the desired patterning control in the dielectric film. In the case of non-silicon containing organic polymers such as SILK™, this is not as difficult to achieve and may be the preferred approach. However, in the case of Si-containing dielectric materials such as SICOH, it is difficult to obtain high etch selectivity to any common hardmask materials, including metal nitrides. It becomes necessary to modify the conventional RIE chemistries or thicken the hardmask layers to the point where SiCOH pattern integrity is lost.
The line-first approach suffers from the difficulty of printing vias inside lines, especially at small dimensions. The reason for this difficulty is that the via imaging layer must planarize above a variety of line trench patterns at different pattern densities, leading to variation in this imaging layer thickness in various structures. It becomes difficult or impossible to define a photolithographic dose and focus process window that can image simultaneously all vias in all line pattern situations. As the via becomes ever smaller in size, it becomes ever more difficult to expose and develop out a via image through the extra thickness of resist that fills in, and becomes planar over, the line structure. Moreover, resist poisoning may continue to be a problem with this approach, as the already-etched line trenches expose the low-k dielectric to the via imaging layer, allowing amines, if present, to and poison this imaging layer.
Photoresist poisoning is a problem well known in the industry. Others skilled in the art have been unsuccessful in attempts to produce a barrier layer which prevents poisoning but does not damage planarizing material during its deposition. Some have therefore abandoned the via-first method, and are typically using hardmask schemes to circumvent poisoning. For example, the methods described in U.S. Pat. No. 6,316,167 and U.S. Published Application No. 2002/0012876 by Angelopoulos et al., the disclosures of which are incorporated herein by reference, use a vapor deposited layer (R:C:H:X) as a multifunctional layer: planarization layer, arc layer, and hardmask layer. The vapor deposited film (R:C:H:X) is said to be compatible with resist, and therefore does not cause poisoning. The vapor deposited layer (R:C:H:X) becomes a permanent film on the device, which necessitates the additional requirement that the layer must also be a low-k material if it is to be used in state of the art devices. It is believed to be ever more difficult to find a material that meets all these requirements. There is currently not a known strip process for this material that would be compatible with patterned low-k dielectrics. Care must be used when selecting films to meet all of these requirements. For example, it has been discovered that some R:C:H:X films prevent poisoning while others do not, depending on the exact nature of the film.
In general, circumventing the phenomenon of resist poisoning has placed significant constraints on other elements in the multilevel damascene integration, especially for low-k insulators, that were not the case in previous generations; these constraints are not desired and represent disadvantages. As in the Higashi et al. paper, limitations are placed on choices that do not result in poisoning for the Cu barrier cap, the interlevel dielectric material itself, the etching and stripping chemistries used, the need for caps over the interlevel dielectric, and the choice of the resist imaging layer material itself. It is desirable to decouple the imaging layer from these other integration elements in a manner that does not constrain the choices in those elements, and yet by definition will prevent poisoning.
Thus, there remains a need in the art for a method of forming a dual damascene structure which does not suffer from the problems of photoresist poisoning.